The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 2025

Filed:

Aug. 11, 2021
Applicant:

Sony Semiconductor Solutions Corporation, Kanagawa, JP;

Inventor:

Sachio Akebono, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 25/78 (2023.01); H03F 1/02 (2006.01); H03F 3/45 (2006.01); H03M 1/56 (2006.01); H04N 25/709 (2023.01); H04N 25/76 (2023.01);
U.S. Cl.
CPC ...
H04N 25/78 (2023.01); H03F 1/0205 (2013.01); H03F 3/45179 (2013.01); H03M 1/56 (2013.01); H04N 25/709 (2023.01); H04N 25/7795 (2023.01); H03F 2203/45074 (2013.01);
Abstract

An imaging device according to the present disclosure includes a light-receiving pixel; a reference signal generator; a first amplification section; a second amplification section; a third amplification section; and a counter. The first amplification section is coupled to a first power supply node and a second power supply node. The first amplification section performs a comparison operation on the basis of a pixel signal and a reference signal. The first amplification section outputs a signal corresponding to a result of the comparison to a first node. The second amplification section includes a first transistor and a first load circuit. The first transistor includes a gate coupled to the first node, a drain coupled to a second node, and a source coupled to the second power supply node. The third amplification section includes a second transistor and a first switch. The second transistor includes a gate coupled to the second node, a source coupled to the first power supply node, and a drain coupled to a third node. The first switch applies a predetermined voltage to the third node by being turned on. The counter is coupled to a third power supply node and a fourth power supply node. The counter stops a count operation on the basis of a voltage of the third node.


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