Clocking scheme for reduced noise in continuous-time sigma-delta adcs preliminary class

Abstract

A circuit for a feedback system incorporates a gating mechanism to reduce flicker noise (e.g., a source for bias instability within a MEMS device) at a digital output. The gating mechanism generates a gating pulse with a delay period (e.g., a common, or fixed, delay including symmetrical rising and falling edge delays) that overrides internal delays (e.g., asymmetrical rising and falling edge delays) of a phase generator to prevent propagation delay (e.g., delay affected by jitter) from reaching subsequent feedback components (e.g., a digital-to-analog converter (DAC)) and contributing to the generation of flicker noise within the system.