The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 2025

Filed:

Feb. 17, 2022
Applicant:

Psemi Corporation, San Diego, CA (US);

Inventor:

Tero Tapio Ranta, San Diego, CA (US);

Assignee:

PSEMI CORPORATION, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/16 (2006.01); H01F 21/12 (2006.01); H01G 4/002 (2006.01); H01G 7/00 (2006.01); H01L 23/522 (2006.01); H01L 27/06 (2006.01); H01L 27/12 (2006.01); H01L 49/02 (2006.01); H03H 7/01 (2006.01); H03H 7/38 (2006.01); H03H 11/28 (2006.01); H03J 3/20 (2006.01); H03K 17/10 (2006.01); H03K 17/687 (2006.01); H03M 1/10 (2006.01); H03M 1/80 (2006.01);
U.S. Cl.
CPC ...
H03K 17/162 (2013.01); H01F 21/12 (2013.01); H01G 4/002 (2013.01); H01G 7/00 (2013.01); H01L 23/5223 (2013.01); H01L 27/0629 (2013.01); H01L 27/1203 (2013.01); H01L 28/60 (2013.01); H03H 7/0153 (2013.01); H03H 7/38 (2013.01); H03H 11/28 (2013.01); H03J 3/20 (2013.01); H03K 17/102 (2013.01); H03K 17/687 (2013.01); H03M 1/1061 (2013.01); H03J 2200/10 (2013.01); H03M 1/804 (2013.01);
Abstract

A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF− terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB.


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