The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 14, 2025
Filed:
Mar. 28, 2022
Chipone Technology (Beijing) Co., Ltd., Beijing, CN;
Tianhao Chen, Beijing, CN;
Junjie Wu, Beijing, CN;
CHIPONE TECHNOLOGY (BEIJING) CO., LTD., Beijing, CN;
Abstract
Disclosed is an circuit for preventing latch-up, comprising a first transistor, a second transistor of a type opposite to that of the first transistor, and a control circuit, wherein a control terminal of the first transistor receives a first control voltage and a first terminal of the first transistor receives a first supply voltage; a control terminal of the second transistor receives a second control voltage, and is connected to a second terminal of the first transistor; a first terminal of the second transistor is connected to the control terminal of the first transistor, and a second terminal of the second transistor receives a second supply voltage. The control circuit is coupled on a path formed by the first transistor and the second transistor between the first supply voltage and the second supply voltage for disconnecting the path when the first control voltage and/or the second control voltage is out of a predetermined range. The circuit for preventing latch-up provided by the present invention, by introducing the control circuit on the path formed by the first transistor and the second transistor between the first supply voltage and the second supply voltage, can disconnect the path when the first control voltage and/or the second control voltage is out of the predetermined range, so that a latch-up effect is prevented from occurring during power-on phase.