The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 2025

Filed:

Nov. 16, 2023
Applicant:

Aurora Operations, Inc., Mountain View, CA (US);

Inventors:

James Ferrara, Oakland, CA (US);

Pruthvi Jujjavarapu, Palo Alto, CA (US);

Sen Lin, Mountain View, CA (US);

Xue Liu, San Jose, CA (US);

Andrew Steil Michaels, Los Altos, CA (US);

Parth Panchal, San Jose, CA (US);

Zhizhong Tang, Palo Alto, CA (US);

Assignee:

AURORA OPERATIONS, INC., Pittsburgh, PA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01S 17/88 (2006.01); G02B 6/122 (2006.01); H01S 5/00 (2006.01); G02B 6/12 (2006.01);
U.S. Cl.
CPC ...
H01S 5/0014 (2013.01); G01S 17/88 (2013.01); G02B 6/1225 (2013.01); G02B 2006/12121 (2013.01); H01S 2301/17 (2013.01);
Abstract

A LIDAR sensor system for a vehicle includes a silicon photonics substrate. The silicon photonics substrate includes: a semiconductor wafer; one or more surface features on a first surface of the semiconductor wafer; and a photoresist layer formed on the first surface of the semiconductor wafer, wherein the photoresist layer includes a laminated dry film. The silicon photonics substrate can be manufactured by obtaining a semiconductor wafer having one or more surface features; applying a dry film photoresist layer to a first surface of the semiconductor wafer; performing an adhesion bake process on the semiconductor wafer; developing the dry film photoresist layer to produce one or more developed regions in the dry film photoresist layer; and forming one or more solder bumps in the one or more developed regions.


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