The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 2025

Filed:

Oct. 25, 2021
Applicant:

Board of Trustees of the University of Arkansas, Little Rock, AR (US);

Inventors:

Shui-Qing Yu, Fayetteville, AR (US);

Gregory J. Salamo, Fayetteville, AR (US);

Rahul Kumar, Fayetteville, AR (US);

Samir K. Saha, Fayetteville, AR (US);

Yang Zhang, Fayetteville, AR (US);

Samir M. El-Ghazaly, Fayetteville, AR (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 31/0352 (2006.01); H01L 21/02 (2006.01); H01L 27/146 (2006.01); H01L 31/0304 (2006.01); H04N 5/32 (2023.01);
U.S. Cl.
CPC ...
H01L 27/14658 (2013.01); H01L 21/0242 (2013.01); H01L 21/02433 (2013.01); H01L 21/02463 (2013.01); H01L 21/02505 (2013.01); H01L 21/02507 (2013.01); H01L 21/02516 (2013.01); H01L 21/02546 (2013.01); H01L 21/02609 (2013.01); H01L 21/02631 (2013.01); H01L 31/0304 (2013.01); H01L 31/035209 (2013.01); H04N 5/32 (2013.01);
Abstract

An integrated microwave photonics (IMWP) apparatus is provided using sapphire as a platform. The IMWP apparatus includes: a sapphire substrate having a step-terrace surface; and a III-V stack layer epitaxially grown on the sapphire substrate. The III-V stack layer includes: a first III-V layer disposed on the sapphire substrate; a low temperature (LT) III-V buffer layer disposed on the first III-V layer; multiple second III-V layers disposed and stacked on the LT III-V buffer layer; a third III-V layer disposed on the second III-V layers; a III-V quantum well layer disposed on the third III-V layers; and a fourth III-V layer disposed on the III-V quantum well layer. The second III-V layers are respectively annealed. A growth temperature of the LT III-V layer and a growth temperature of the III-V quantum well layer are lower than a growth temperature of each of the first, second, third and fourth III-V layers.


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