The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 2025

Filed:

Sep. 29, 2021
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventor:

Sung Hyun Hwang, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/16 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/16 (2013.01); G11C 16/3459 (2013.01);
Abstract

A memory device includes a first sub-block including word lines, a second sub-block including word lines, and a peripheral circuit configured to apply voltages to the word lines of the first sub-block and the word lines of the second sub-block. The memory device also includes control logic configured to control the peripheral circuit to perform a partial program operation of storing data in the first sub-block, when a plurality of memory cells included in the first sub-block are erased and a plurality of memory cells included in the second sub-block are programmed. The control logic includes a program operation controller for controlling the peripheral circuit to apply a verify operation to a selected word line of the word lines of the first sub-block and then apply a voltage having a constant level to the word lines of the second sub-block in the partial program operation.


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