Semiconductor memory devices and controller including adjustable strobe delay

Abstract

A semiconductor device according to an embodiment of the present invention which can rapidly output data while being relatively low cost includes: a plurality of memory each including: a strobe signal transmission path having, in this order, a strobe input terminal, a strobe delay circuit, and a strobe output terminal; a plurality of data output circuits connected to a downstream side of the strobe delay circuit of the strobe signal transmission path; and a data output bus connected to the plurality of data output circuits; and a controller including: a strobe circuit which inputs the strobe signal to the strobe input terminal; a data buffer circuit which temporarily stores the data outputted from the data output terminal; and a delay adjustment circuit which adjusts a delay amount of the strobe delay circuit so as to decrease a difference between the memory in delay of the strobe signal outputted from the strobe output terminal relative to the strobe signal outputted from the strobe circuit.