The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 14, 2025
Filed:
Aug. 22, 2018
Syntiant, Irvine, CA (US);
Kurt F. Busch, Laguna Hills, CA (US);
Jeremiah H. Holleman, III, Irvine, CA (US);
Pieter Vorenkamp, Laguna Beach, CA (US);
Stephen W. Bailey, Irvine, CA (US);
SYNTIANT, Irvine, CA (US);
Abstract
A computerized method comprising receiving, by a simulator logic, inputs including: (i) at least one circuit-level characteristic, and (ii) an architectural description of a neural network, modeling, by the simulator logic, execution of the neural network described in the inputs to obtain results representative of what an analog implementation of the neural network would produce, and determining, by the simulator logic, an accuracy of computational analog elements within the analog implementation of the neural network based on the results obtained during modeling of the neural network is described. In some embodiments, the circuit-level characteristic includes thermal or flicker noise, an inaccuracy of weights between nodes within the neural network, or a frequency response variations of an integrated circuit. Additionally, the circuit-level characteristic can be obtained through simulation of an integrated circuit based on technology-specific measurements of the integrated circuit.