Hardware architecture determination based on a neural network and a network compilation process

Abstract

The described techniques provide for an automated process of hardware design using main applications (e.g., use cases) and a modeling heuristic of a compiler. Hardware may be optimized and designed based on the knowledge of the compiler for the hardware and firmware information. For instance, a user may define constraints (e.g., area constraints, power constraints, performance constraints, accuracy degradation constraints, etc.) and the changes of compilation heuristics and hardware parameters may be optimized to efficiently achieve the user defined constraints. Accordingly, hardware configuration parameters may be optimized based on the neural network's compilation process (e.g., actual compiler constraints) and optimization of power, performance, and area (PPA) constraints (e.g., user defined constraints). Specific neural processor (SNP) hardware may thus be designed based on the optimized hardware configuration parameters (e.g., via modeling heuristics of its compiler and main applications informed via user defined constraints or PPA constraints).