The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 2025

Filed:

Mar. 17, 2021
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Yury Uralsky, Los Gatos, CA (US);

Henry Moreton, Woodside, CA (US);

Matthijs de Smedt, San Jose, CA (US);

Lei Yang, Santa Clara, CA (US);

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); G06T 1/20 (2006.01); G06T 1/60 (2006.01);
U.S. Cl.
CPC ...
G06F 9/5038 (2013.01); G06F 9/5011 (2013.01); G06F 9/5055 (2013.01); G06F 9/5072 (2013.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01);
Abstract

The present technology augments the GPU compute model to provide system-provided data marshalling characteristics of graphics pipelining to increase efficiency and reduce overhead. A simple scheduling model based on scalar counters (e.g., semaphores) abstract the availability of hardware resources. Resource releases can be done programmatically, and a system scheduler only needs to track the states of such counters/semaphores to make work launch decisions. Semantics of the counters/semaphores are defined by an application, which can use the counters/semaphores to represent the availability of free space in a memory buffer, the amount of cache pressure induced by the data flow in the network, or the presence of work items to be processed.


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