Method and system for providing configuration data to a field-programmable gate array via multiple protocol modes

Abstract

A hybrid mode system containing an external device and a field-programmable gate array ('FPGA') capable of providing configuration data to FPGA via a hybrid communication channel is disclosed. The system is able to identify a first communication protocol in accordance with at least a portion of address bits presented on a serial data line (“SDA”) wherein SDA is used as a connection between FPGA and the external device. The clock signals for receiving data are adjusted to a first clock frequency in accordance with the first communication protocol and clock cycles presented on a serial clock line (“SCL”). SCL is used to connection between FPGA and the external device. After transmitting the configuration data, a portion of FPGA is programmed to perform user-defined logic functions in response to the configuration data.