Apparatus and method for cache invalidation

Abstract

There is provided an apparatus, medium and method for cache invalidation. The apparatus comprises a cache having a plurality of entries grouped into a plurality of entry sets. Each entry of the plurality of entries identifies an address range having one of a plurality of predetermined address range sizes. The apparatus further comprises cache invalidation circuitry responsive to a cache invalidation request indicating an address invalidation range to trigger invalidation of entries in the cache that overlap the address invalidation range. The cache invalidation circuitry is configured to operate in one of a plurality of invalidation modes based on the address invalidation range and cache occupancy information indicating address range sizes identified by the plurality of entries in the cache. The plurality of invalidation modes comprise: an entry-driven invalidation mode in which the cache invalidation circuitry is configured, for each entry of the plurality of entries and in response to a determination that the address invalidation range overlaps the address range identified by that entry, to invalidate that entry; and an invalidation-range-driven invalidation mode in which the cache invalidation circuitry is configured to generate a set of address range sizes based on the address range sizes indicated in the cache occupancy information and, for each given address range size, to generate one or more cache indexes from the address invalidation range in dependence on the given address range size, each of the cache indexes identifying a corresponding entry set of the plurality of entry sets, and for each corresponding entry set to invalidate entries in dependence on whether the address range identified by those entries overlaps the address invalidation range.