The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 2025

Filed:

Nov. 22, 2022
Applicant:

Gopro, Inc., San Mateo, CA (US);

Inventors:

Alexis Lefebvre, Paris, FR;

Vincent Vacquerie, Longnes, FR;

Assignee:

GoPro, Inc., San Mateo, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 1/10 (2006.01); G06F 1/3225 (2019.01); G06F 1/3296 (2019.01); G06F 1/3203 (2019.01);
U.S. Cl.
CPC ...
G06F 1/3225 (2013.01); G06F 1/10 (2013.01); G06F 1/3296 (2013.01); G06F 1/3203 (2013.01);
Abstract

Systems and methods are disclosed for dynamic power allocation for memory using multiple interleaving patterns. For example, a system may include a set of memory devices, including a first subset and a second subset, and a memory management circuitry configured to translate virtual addresses into physical addresses of memory locations in the set of memory devices using a first interleaving pattern when operating in a first mode; and translate virtual addresses using a second interleaving pattern when operating in a second mode. The first and second interleaving patterns both map virtual addresses in a first range exclusively to memory devices in the first subset. The first interleaving pattern maps virtual addresses in a second range to memory devices in the first subset and in the second subset. The second interleaving pattern maps virtual addresses in the second range exclusively to memory devices in the first subset.


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