The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 2025

Filed:

Feb. 02, 2023
Applicant:

Delphi Technologies Ip Limited, St. Michael, BB;

Inventor:

Jack Lavern Glenn, Union Pier, MI (US);

Assignee:

Borg Warner US Technologies LLC, Wilmington, DE (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H02P 1/00 (2006.01); B60L 3/00 (2019.01); B60L 15/00 (2006.01); B60L 15/08 (2006.01); B60L 50/40 (2019.01); B60L 50/51 (2019.01); B60L 50/60 (2019.01); B60L 50/64 (2019.01); B60L 53/20 (2019.01); B60L 53/22 (2019.01); B60L 53/62 (2019.01); B60R 16/02 (2006.01); G01R 15/20 (2006.01); G06F 1/08 (2006.01); G06F 13/40 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/15 (2006.01); H01L 23/367 (2006.01); H01L 23/373 (2006.01); H01L 23/40 (2006.01); H01L 23/467 (2006.01); H01L 23/473 (2006.01); H01L 23/495 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H01L 25/07 (2006.01); H01L 29/66 (2006.01); H02J 7/00 (2006.01); H02M 1/00 (2006.01); H02M 1/08 (2006.01); H02M 1/084 (2006.01); H02M 1/088 (2006.01); H02M 1/12 (2006.01); H02M 1/32 (2007.01); H02M 1/42 (2007.01); H02M 1/44 (2007.01); H02M 3/335 (2006.01); H02M 7/00 (2006.01); H02M 7/537 (2006.01); H02M 7/5387 (2007.01); H02M 7/5395 (2006.01); H02P 27/06 (2006.01); H02P 27/08 (2006.01); H02P 29/024 (2016.01); H02P 29/68 (2016.01); H05K 1/14 (2006.01); H05K 1/18 (2006.01); H05K 5/02 (2006.01); H05K 7/20 (2006.01); B60L 15/20 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
B60L 50/60 (2019.02); B60L 3/003 (2013.01); B60L 15/007 (2013.01); B60L 15/08 (2013.01); B60L 50/40 (2019.02); B60L 50/51 (2019.02); B60L 50/64 (2019.02); B60L 53/20 (2019.02); B60L 53/22 (2019.02); B60L 53/62 (2019.02); B60R 16/02 (2013.01); G01R 15/20 (2013.01); G06F 1/08 (2013.01); G06F 13/4004 (2013.01); H01L 21/4882 (2013.01); H01L 23/15 (2013.01); H01L 23/3672 (2013.01); H01L 23/3675 (2013.01); H01L 23/3735 (2013.01); H01L 23/4006 (2013.01); H01L 23/467 (2013.01); H01L 23/473 (2013.01); H01L 23/49562 (2013.01); H01L 23/5383 (2013.01); H01L 24/32 (2013.01); H01L 24/33 (2013.01); H01L 25/072 (2013.01); H01L 25/50 (2013.01); H01L 29/66553 (2013.01); H02J 7/0063 (2013.01); H02M 1/0009 (2021.05); H02M 1/0054 (2021.05); H02M 1/08 (2013.01); H02M 1/084 (2013.01); H02M 1/088 (2013.01); H02M 1/123 (2021.05); H02M 1/32 (2013.01); H02M 1/322 (2021.05); H02M 1/327 (2021.05); H02M 1/4258 (2013.01); H02M 1/44 (2013.01); H02M 3/33523 (2013.01); H02M 7/003 (2013.01); H02M 7/537 (2013.01); H02M 7/5387 (2013.01); H02M 7/53871 (2013.01); H02M 7/53875 (2013.01); H02M 7/5395 (2013.01); H02P 27/06 (2013.01); H02P 27/08 (2013.01); H02P 27/085 (2013.01); H02P 29/024 (2013.01); H02P 29/027 (2013.01); H02P 29/68 (2016.02); H05K 1/145 (2013.01); H05K 1/181 (2013.01); H05K 1/182 (2013.01); H05K 5/0247 (2013.01); H05K 7/20154 (2013.01); H05K 7/2049 (2013.01); H05K 7/20854 (2013.01); H05K 7/209 (2013.01); H05K 7/20927 (2013.01); B60L 15/20 (2013.01); B60L 2210/30 (2013.01); B60L 2210/40 (2013.01); B60L 2210/42 (2013.01); B60L 2210/44 (2013.01); B60L 2240/36 (2013.01); G06F 2213/40 (2013.01); H01L 2023/405 (2013.01); H01L 2023/4087 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/33181 (2013.01); H02J 2207/20 (2020.01); H02P 2207/05 (2013.01); H03K 19/20 (2013.01); H05K 2201/042 (2013.01); H05K 2201/10166 (2013.01);
Abstract

A system includes: an inverter including: a first galvanic interface to separate a first high voltage area from a low voltage area; a first low voltage controller in the low voltage area, the first low voltage controller configured to send a first control signal using the first galvanic interface to a first high voltage controller in the first high voltage area; a second galvanic interface to separate a second high voltage area from the low voltage area; and a second low voltage controller in the low voltage area, the first low voltage controller configured to send a second control signal using the second galvanic interface to a second high voltage controller in the second high voltage area, wherein the second low voltage controller is configured to provide an output latch signal to the first low voltage controller and receive an input latch signal from the first low voltage controller.


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