The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2025

Filed:

Apr. 25, 2022
Applicant:

Lg Display Co., Ltd., Seoul, KR;

Inventors:

DaeKyung Kim, Paju-si, KR;

JaeSung Jeon, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10K 59/131 (2023.01); H10K 59/121 (2023.01); H10K 59/123 (2023.01); H10K 59/124 (2023.01); H10K 77/10 (2023.01); H01L 27/12 (2006.01); H10K 50/84 (2023.01); H10K 50/86 (2023.01); H10K 59/40 (2023.01); H10K 102/00 (2023.01);
U.S. Cl.
CPC ...
H10K 77/111 (2023.02); H10K 59/1213 (2023.02); H10K 59/123 (2023.02); H10K 59/124 (2023.02); H10K 59/131 (2023.02); H01L 27/1218 (2013.01); H01L 27/124 (2013.01); H01L 27/1248 (2013.01); H10K 50/841 (2023.02); H10K 50/86 (2023.02); H10K 59/40 (2023.02); H10K 2102/311 (2023.02);
Abstract

A flexible electroluminescent display apparatus can include a flexible substrate including an active area and a bending area extending from the active area; a thin film transistor disposed on the active area and including a semiconductor layer, a gate electrode, a source electrode and a drain electrode; an planarization layer disposed on the thin film transistor; a light emitting element disposed on the planarization layer in the active area and connected to the thin film transistor through a connection electrode; and a first wiring line and a second wiring line disposed in the bending area, in which the first wiring line, the source electrode and the drain electrode are configured as a same layer, and the second wiring line and the connection electrode are configured as a same layer, and the first wiring line and the second wiring line are directly connected to each other.


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