The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2025

Filed:

Oct. 27, 2023
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventor:

Jumpei Sato, Kawasaki Kanagawa, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/20 (2023.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); G11C 16/30 (2006.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01);
U.S. Cl.
CPC ...
H10B 43/40 (2023.02); G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/30 (2013.01); H10B 43/20 (2023.02); H10B 43/35 (2023.02);
Abstract

In a semiconductor memory device, a first plane includes a first memory cell array provided above a substrate in a first direction. A first power supply circuit is provided between the substrate and the first memory cell array, and a first sense amplifier is provided between the substrate and the first memory cell array. A second plane includes a second memory cell array provided above the substrate and a second power supply circuit provided between the substrate and the second memory cell array. A second sense amplifier is provided between the substrate and the second memory cell array. When viewed in the first direction, the first power supply circuit and the first sense amplifier overlap the first memory cell array, and the second power supply circuit and the second sense amplifier overlap the second memory cell array.


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