The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 07, 2025
Filed:
Nov. 13, 2020
Applicant:
Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;
Inventors:
Hitoshi Kunitake, Isehara, JP;
Satoru Ohshita, Atsugi, JP;
Kazuki Tsuda, Atsugi, JP;
Tatsuya Onuki, Atsugi, JP;
Assignee:
Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/40 (2023.01); G11C 16/08 (2006.01); H10B 43/27 (2023.01);
U.S. Cl.
CPC ...
H10B 43/40 (2023.02); G11C 16/08 (2013.01); H10B 43/27 (2023.02);
Abstract
A memory device with a small number of wirings using a NAND flash memory having a three-dimensional structure with a large number of stacked memory cell layers is provided. A decoder is formed using an OS transistor. An OS transistor can be formed by a method such as a thin film method, whereby the decoder can be provided to be stacked above the NAND flash memory having a three-dimensional structure. This can reduce the number of wirings provided substantially perpendicular to the memory cell layers.