The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2025

Filed:

Apr. 20, 2023
Applicant:

Guangzhou Tyrafos Semiconductor Technologies Co., Ltd, Guangzhou, CN;

Inventors:

Ping-Hung Yin, Taipei, TW;

Jia-Shyang Wang, Miaoli County, TW;

Yu-Hsiang Wang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 25/78 (2023.01); G06F 1/08 (2006.01); H01L 25/075 (2006.01); H01L 25/18 (2023.01); H01L 27/146 (2006.01); H03K 19/0185 (2006.01); H03L 7/099 (2006.01); H04N 25/60 (2023.01); H04N 25/627 (2023.01); H04N 25/63 (2023.01); H04N 25/709 (2023.01); H04N 25/76 (2023.01); H04N 25/77 (2023.01); H04N 25/772 (2023.01); H04N 25/778 (2023.01);
U.S. Cl.
CPC ...
H04N 25/78 (2023.01); G06F 1/08 (2013.01); H01L 25/0753 (2013.01); H01L 25/18 (2013.01); H01L 27/14612 (2013.01); H01L 27/14632 (2013.01); H01L 27/14636 (2013.01); H03K 19/018521 (2013.01); H03L 7/099 (2013.01); H04N 25/60 (2023.01); H04N 25/627 (2023.01); H04N 25/63 (2023.01); H04N 25/709 (2023.01); H04N 25/77 (2023.01); H04N 25/772 (2023.01); H04N 25/778 (2023.01); H04N 25/7795 (2023.01);
Abstract

An image sensor and an operating method thereof are provided. The image sensor includes a first pixel circuit, a first column readout circuit, and a second column readout circuit. The first pixel circuit includes a first pixel unit, a first transfer transistor, a first reset transistor, a first readout transistor, and a first capacitor. The first column readout circuit includes a first circuit node. The second column readout circuit includes a bias transistor. A first terminal of the first reset transistor and a first terminal of the first readout transistor are coupled to the first circuit node, and a second terminal of the first readout transistor is coupled to the bias transistor.


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