The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2025

Filed:

Apr. 13, 2023
Applicant:

Guangzhou Tyrafos Semiconductor Technologies Co., Ltd, Guangzhou, CN;

Inventors:

Ping-Hung Yin, Taipei, TW;

Jia-Shyang Wang, Miaoli County, TW;

Jia-Sian Lyu, Pingtung County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04N 25/78 (2023.01); G06F 1/08 (2006.01); H01L 25/075 (2006.01); H01L 25/18 (2023.01); H01L 27/146 (2006.01); H03K 19/0185 (2006.01); H03L 7/099 (2006.01); H04N 25/60 (2023.01); H04N 25/627 (2023.01); H04N 25/63 (2023.01); H04N 25/709 (2023.01); H04N 25/76 (2023.01); H04N 25/77 (2023.01); H04N 25/772 (2023.01); H04N 25/778 (2023.01);
U.S. Cl.
CPC ...
H04N 25/78 (2023.01); G06F 1/08 (2013.01); H01L 25/0753 (2013.01); H01L 25/18 (2013.01); H01L 27/14612 (2013.01); H01L 27/14632 (2013.01); H01L 27/14636 (2013.01); H03K 19/018521 (2013.01); H03L 7/099 (2013.01); H04N 25/60 (2023.01); H04N 25/627 (2023.01); H04N 25/63 (2023.01); H04N 25/709 (2023.01); H04N 25/77 (2023.01); H04N 25/772 (2023.01); H04N 25/778 (2023.01); H04N 25/7795 (2023.01);
Abstract

An image sensor, a level shifter circuit, and an operation method thereof are provided. The image sensor includes a pixel circuit and a pixel driving circuit. The pixel driving circuit includes first, second, third, fourth, fifth, and sixth transistors. A first terminal of the first transistor is coupled to a first voltage. A first terminal of the second transistor is coupled to the first voltage, and a control terminal of the second transistor is coupled to a control terminal of the first transistor and a second terminal of the first transistor. A first terminal of the third transistor is coupled to the second terminal of the first transistor, and a second terminal of the third transistor is coupled to a ground voltage. A first terminal of the fourth transistor is coupled to a second terminal of the second transistor and an output terminal.


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