The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2025

Filed:

Oct. 18, 2023
Applicant:

Nippon Hoso Kyokai, Tokyo, JP;

Inventors:

Shunsuke Iwamura, Tokyo, JP;

Atsuro Ichigaya, Tokyo, JP;

Shinichi Sakaida, Tokyo, JP;

Assignee:

NIPPON HOSO KYOKAI, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 19/61 (2014.01); H04N 19/105 (2014.01); H04N 19/117 (2014.01); H04N 19/12 (2014.01); H04N 19/124 (2014.01); H04N 19/147 (2014.01); H04N 19/176 (2014.01); H04N 19/44 (2014.01); H04N 19/46 (2014.01); H04N 19/593 (2014.01); H04N 19/625 (2014.01);
U.S. Cl.
CPC ...
H04N 19/105 (2014.11); H04N 19/117 (2014.11); H04N 19/12 (2014.11); H04N 19/124 (2014.11); H04N 19/147 (2014.11); H04N 19/176 (2014.11); H04N 19/45 (2014.11); H04N 19/46 (2014.11); H04N 19/593 (2014.11); H04N 19/619 (2014.11); H04N 19/625 (2014.11);
Abstract

An image encoding device for block-dividing and encoding an original image of a frame unit constituting a moving image is disclosed that includes a predictor circuitry configured to generate a predicted image, a weighted average processor configured to generate a block of a new predicted image, a prediction residual signal generator circuitry configured to calculate an error of each prediction signal of the block of the predicted image and to generate a prediction residual signal, a sub-block divider circuitry configured to divide the prediction residual signal configured to divide the predict residual signal, and a transformation selection applier circuitry configured to selectively apply a plurality of types of transformation processes for a divided sub-block of the prediction residual signal.


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