The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2025

Filed:

Nov. 08, 2021
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Yann Mignot, Slingerlands, NY (US);

Su Chen Fan, Cohoes, NY (US);

Jing Guo, Niskayuna, NY (US);

Lijuan Zou, Slingerlands, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 29/08 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7827 (2013.01); H01L 29/0847 (2013.01); H01L 29/6656 (2013.01); H01L 29/66666 (2013.01); H01L 29/7851 (2013.01);
Abstract

Techniques for area scaling of contacts in VTFET devices are provided. In one aspect, a VTFET device includes: a fin(s); a bottom source/drain region at a base of the fin(s); a gate stack alongside the fin(s); a top source/drain region present at a top of the fin(s); a bottom source/drain contact to the bottom source/drain region; and a gate contact to the gate stack, wherein the bottom source drain and gate contacts each includes a top portion having a width W1over a bottom portion having a width W2, wherein W2<W1, and wherein a sidewall along the top portion is discontinuous with a sidewall along the bottom portion. The bottom portion having the width W2is present alongside the gate stack and the top source/drain region. A method of forming a VTFET device is also provided.


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