The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2025

Filed:

Sep. 08, 2021
Applicant:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Inventor:

Tatsuo Shimizu, Shinagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); B60L 53/20 (2019.01); H01L 29/16 (2006.01); H01L 29/167 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); B66B 11/04 (2006.01); H01L 21/04 (2006.01); H01L 29/04 (2006.01); H01L 29/423 (2006.01); H02P 27/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1045 (2013.01); B60L 53/20 (2019.02); H01L 29/167 (2013.01); H01L 29/66068 (2013.01); H01L 29/7813 (2013.01); B66B 11/043 (2013.01); H01L 21/045 (2013.01); H01L 29/045 (2013.01); H01L 29/1608 (2013.01); H01L 29/4236 (2013.01); H01L 29/7825 (2013.01); H02P 27/06 (2013.01);
Abstract

A semiconductor device of embodiments includes: a silicon carbide layer having a first face and a second face and including a first trench, a second trench having a distance of 100 nm or less from the first trench, a first silicon carbide region of n-type, a second silicon carbide region of p-type between the first trench and the second trench, a third silicon carbide region of n-type between the second silicon carbide region and the first face, a fourth silicon carbide region between the first trench and the second silicon carbide region and containing oxygen, and a fifth silicon carbide region between the second trench and the second silicon carbide region and containing oxygen; a first gate electrode in the first trench; a second gate electrode in the second trench; a first gate insulating layer; a second gate insulating layer; a first electrode; and a second electrode.


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