The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2025

Filed:

Feb. 15, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventor:

In-Jae Lee, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 25/16 (2023.01); H01R 13/66 (2006.01); H01L 23/00 (2006.01); H01L 23/24 (2006.01); H01L 23/498 (2006.01); H01R 24/62 (2011.01);
U.S. Cl.
CPC ...
H01L 25/165 (2013.01); H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 23/3121 (2013.01); H01R 13/665 (2013.01); H01L 23/24 (2013.01); H01L 23/49811 (2013.01); H01L 24/32 (2013.01); H01L 24/33 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/33181 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73215 (2013.01); H01L 2224/73265 (2013.01); H01R 24/62 (2013.01);
Abstract

A semiconductor package includes a package substrate, a semiconductor chip on the package substrate, the semiconductor chip including a logic chip and a memory stack structure on the logic chip, a connector and a connector terminal below the package substrate, a molding layer that covers the semiconductor chip, the molding layer having a recess region on a top surface of the molding layer, a housing that covers the molding layer, and an air gap on the semiconductor chip, the air gap being defined by the housing and the recess region of the molding layer, and the molding layer separating the air gap from the memory stack structure of the semiconductor chip.


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