The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2025

Filed:

Nov. 26, 2021
Applicants:

Chengdu Boe Optoelectronics Technology Co., Ltd., Sichuan, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Gansong Yang, Beijing, CN;

Yunpeng Zhang, Beijing, CN;

Ming Yang, Beijing, CN;

Yanhong Ding, Beijing, CN;

Ke Liu, Beijing, CN;

Miao Liu, Beijing, CN;

Xing Yao, Beijing, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/3233 (2016.01); G09G 3/3266 (2016.01);
U.S. Cl.
CPC ...
G09G 3/3233 (2013.01); G09G 3/3266 (2013.01); G09G 2300/0408 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0281 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G09G 2320/045 (2013.01);
Abstract

A display substrate is provided to include: a base substrate including a display area and a peripheral area surrounding the display area; pixel units in array are in the display area; a driving module is in the peripheral area and is configured to provide electrical signals for the pixel units, to control the pixel units to operate; the driving module includes driving circuits each provided with a corresponding operating signal line group in the peripheral area; the signal line group includes at least two operating signal lines connected to the corresponding driving circuit, to provide electrical signals thereto; the at least two operating signal lines include first and second clock signal lines; the first clock signal lines for at least two driving circuits are a same first clock signal line; and/or the second clock signal lines for the at least two driving circuits are a same second clock signal line.


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