The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2025

Filed:

Nov. 07, 2022
Applicant:

Perceive Corporation, San Jose, CA (US);

Inventors:

Kenneth Duong, San Jose, CA (US);

Jung Ko, San Jose, CA (US);

Steven L. Teig, Menlo Park, CA (US);

Assignee:

Amazon Technologies, Inc., Seattle, WA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/063 (2023.01); G06F 1/03 (2006.01); G06F 5/01 (2006.01); G06F 7/544 (2006.01); G06F 9/30 (2018.01); G06F 17/10 (2006.01); G06F 17/16 (2006.01); G06N 3/048 (2023.01); G06N 3/06 (2006.01); G06N 3/08 (2023.01); G06N 3/084 (2023.01); G06N 5/04 (2023.01); G06N 5/046 (2023.01); G06N 20/00 (2019.01);
U.S. Cl.
CPC ...
G06N 3/063 (2013.01); G06F 1/03 (2013.01); G06F 5/01 (2013.01); G06F 7/5443 (2013.01); G06F 9/30098 (2013.01); G06F 9/30145 (2013.01); G06F 17/10 (2013.01); G06F 17/16 (2013.01); G06N 3/048 (2023.01); G06N 3/06 (2013.01); G06N 3/08 (2013.01); G06N 3/084 (2013.01); G06N 5/04 (2013.01); G06N 5/046 (2013.01); G06N 20/00 (2019.01);
Abstract

Some embodiments provide a neural network inference circuit (NNIC) for executing a neural network that includes multiple computation nodes at multiple layers. The NNIC includes a set of clusters of core computation circuits and a channel, connecting the core computation circuits, that includes separate segments corresponding to each of the clusters. The NNIC includes a fabric controller circuit, a cluster controller circuit for each of the clusters, and a core controller circuit for each of the core computation circuits. The fabric controller circuit receives high-level neural network instructions from a microprocessor and parses the high-level neural network instructions.


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