The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2025

Filed:

Jun. 30, 2021
Applicant:

Raytheon Company, Waltham, MA (US);

Inventor:

Stephen R. Reid, Ayer, MA (US);

Assignee:

Raytheon Company, Tewksbury, MA (US);

Primary Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 9/48 (2006.01);
U.S. Cl.
CPC ...
G06F 9/4893 (2013.01);
Abstract

A method includes obtaining thermal information and latency information associated with multiple components of at least one semiconductor chip. The latency information identifies multiple latencies associated with multiple applications to be executed by the components of the at least one semiconductor chip. The method also includes scheduling, using a run-time scheduler on the at least one semiconductor chip, execution of the multiple applications by the components of the at least one semiconductor chip. The run-time scheduler utilizes the thermal information and the latency information along with run-time events to determine which components of the at least one semiconductor chip execute the applications over time.


Find Patent Forward Citations

Reid, Stephen. (2025). Run-time schedulers for field programmable gate arrays or other logic devices (U.S. Patent No. 12190152). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12190152

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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