The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2025

Filed:

Apr. 11, 2023
Applicant:

Dell Products L.p., Round Rock, TX (US);

Inventors:

Wei Liu, Austin, TX (US);

Tuyet-Huong Th Nguyen, Cedar Park, TX (US);

Assignee:

Dell Products L.P., Round Rock, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/07 (2006.01);
U.S. Cl.
CPC ...
G06F 11/0793 (2013.01); G06F 11/0745 (2013.01); G06F 11/0787 (2013.01);
Abstract

A PCIe device error handling system includes a BIOS subsystem coupled to a PCIe device and a BMC device. The BIOS subsystem identifies an error in the PCIe device and, in response, begins an SMM that suspends the performance of at least one workload in an operating system, and generates and transmits a PCIe device error information collection instruction associated with the PCIe device to the BMC device. Subsequent to transmitting the PCIe device error information collection instruction, the BIOS subsystem ends the SMM such that the performance of at least one workload is resumed in the operating system. In response to receiving the PCIe device error information collection instruction from the BIOS subsystem, the BMC device retrieves PCIe device error information from the PCIe device while the operating system performs the at least one workload, and stores the PCIe device error information.


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