The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 07, 2025
Filed:
Jan. 06, 2023
Applicant:
SK Hynix Inc., Icheon-si Gyeonggi-do, KR;
Inventors:
Yeon Ho Lee, Icheon-si Gyeonggi-do, KR;
Yong Suk Choi, Icheon-si Gyeonggi-do, KR;
Assignee:
SK hynix Inc., Icheon-si Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/08 (2006.01); G06F 1/10 (2006.01); G06F 1/12 (2006.01);
U.S. Cl.
CPC ...
G06F 1/08 (2013.01); G06F 1/10 (2013.01); G06F 1/12 (2013.01);
Abstract
A clock generating circuit includes a buffer circuit and a phase compensating circuit. The buffer circuit buffers an input clock signal to generate an output clock signal. The phase compensating circuit detects a noise in a power voltage and adjusts, according to the noise of the power voltage, a voltage level of the input clock signal to compensate for a phase change of the output clock signal due to the noise of the power voltage.
Lee, Yeon. (2025). Clock generating circuit and clock distribution network and semiconductor apparatus including the clock generating circuit (U.S. Patent No. 12189416). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12189416
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile