The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2024

Filed:

Mar. 11, 2022
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventor:

Kazuto Ohsawa, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); G11C 11/22 (2006.01); G11C 16/04 (2006.01); H01L 23/522 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); G11C 16/0483 (2013.01); H01L 23/5226 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02);
Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers. Stepped surfaces including vertical sidewalls of the insulating layers are present in a staircase region. Pad stacks are located on the stepped surfaces. Each of the pad stacks includes an insulating pad having a same material composition as the insulating layers, and a dielectric material pad having a different material composition than the insulating layers and having sidewalls that are vertically coincident with sidewalls of the insulating pad. Memory stack structures extend through the alternating stack. Each of the memory stack structures includes a vertical stack of memory elements and a vertical semiconductor channel.


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