The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2024

Filed:

Jun. 29, 2023
Applicant:

Zeno Semiconductor, Inc., Sunnyvale, CA (US);

Inventors:

Yuniarto Widjaja, Cupertino, CA (US);

Zvi Or-Bach, San Jose, CA (US);

Assignee:

Zeno Semiconductor, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); G11C 7/22 (2006.01); G11C 11/39 (2006.01); G11C 11/404 (2006.01); G11C 11/4074 (2006.01); G11C 11/4094 (2006.01); G11C 11/4096 (2006.01); G11C 11/4099 (2006.01); G11C 14/00 (2006.01); H01L 23/528 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/772 (2006.01); H01L 29/78 (2006.01); H01L 29/788 (2006.01); H10B 12/10 (2023.01); G11C 11/04 (2006.01); G11C 11/402 (2006.01);
U.S. Cl.
CPC ...
H10B 12/20 (2023.02); G11C 7/22 (2013.01); G11C 11/39 (2013.01); G11C 11/404 (2013.01); G11C 11/4074 (2013.01); G11C 11/4094 (2013.01); G11C 11/4096 (2013.01); G11C 11/4099 (2013.01); G11C 14/0018 (2013.01); H01L 23/528 (2013.01); H01L 29/0821 (2013.01); H01L 29/1004 (2013.01); H01L 29/1095 (2013.01); H01L 29/66825 (2013.01); H01L 29/66833 (2013.01); H01L 29/772 (2013.01); H01L 29/7841 (2013.01); H01L 29/7881 (2013.01); H10B 12/10 (2023.02); G11C 11/04 (2013.01); G11C 11/4026 (2013.01); G11C 2211/4016 (2013.01);
Abstract

An IC may include an array of memory cells formed in a semiconductor, including memory cells arranged in rows and columns, each memory cell may include a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type, wherein the floating body region is bounded on a first side by a first insulating region having a first thickness and on a second side by a second insulating region having a second thickness, and a gate region above the floating body region and the second insulating region and is insulated from the floating body region by an insulating layer; and control circuitry configured to provide electrical signals to the buried region.


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