The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2024

Filed:

Feb. 22, 2019
Applicant:

Mitsubishi Electric Corporation, Tokyo, JP;

Inventors:

Shiro Hino, Tokyo, JP;

Junichi Nakashima, Tokyo, JP;

Takaaki Tominaga, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/49 (2006.01); H01L 21/04 (2006.01); H01L 21/76 (2006.01); H01L 21/761 (2006.01); H01L 23/482 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/16 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 49/02 (2006.01); H02M 7/00 (2006.01);
U.S. Cl.
CPC ...
H01L 28/10 (2013.01); H01L 21/0465 (2013.01); H01L 21/7602 (2013.01); H01L 21/761 (2013.01); H01L 23/4824 (2013.01); H01L 29/0623 (2013.01); H01L 29/1095 (2013.01); H01L 29/1608 (2013.01); H01L 29/49 (2013.01); H01L 29/66068 (2013.01); H01L 29/7811 (2013.01); H02M 7/003 (2013.01);
Abstract

To provide a technique of reducing gate oscillation while suppressing reduction in switching speed. A semiconductor device according to the technique disclosed in the present description includes: a first gate electrode in an active region; a gate pad in a first region different from the active region in a plan view; and a first gate line electrically connecting the first gate electrode and the gate pad to each other. The first gate line is formed into a spiral shape. The first gate line is made of a different type of material from the first gate electrode.


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