The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2024

Filed:

Jul. 18, 2019
Applicant:

Ultramemory Inc., Tokyo, JP;

Inventor:

Fumitake Okutsu, Tokyo, JP;

Assignee:

ULTRAMEMORY, INC., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/367 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0652 (2013.01); H01L 21/4857 (2013.01); H01L 21/4882 (2013.01); H01L 21/565 (2013.01); H01L 23/3675 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H01L 2224/16145 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01);
Abstract

A semiconductor module that enables reduction of manufacturing costs, a method for manufacturing the same, and a semiconductor module mounting body. The semiconductor module having a plurality of stacked dies includes: a first die; a second die disposed side by side with respect to the first die in a direction intersecting with a stacking direction; a third die disposed in the stacking direction, so as to straddle the first die and the second die and that is electrically connected to wiring surfaces of the first die and the second die opposing the third die; projection terminals projecting from the wiring surfaces of the first die and the second die and that project in a space adjacent to at least one of side surfaces of the third die in the direction intersecting with the stacking direction; and rewiring layers disposed so as to overlap with the projection terminals.


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