The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2024

Filed:

Aug. 22, 2022
Applicant:

Huawei Technologies Co., Ltd., Guangdong, CN;

Inventors:

Huifang Jiao, Shenzhen, CN;

Ran He, Yokohama, JP;

Luming Fan, Shenzhen, CN;

Yue Pan, Shenzhen, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/12 (2006.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01); G11C 8/08 (2006.01);
U.S. Cl.
CPC ...
G11C 7/12 (2013.01); G11C 7/067 (2013.01); G11C 7/1012 (2013.01); G11C 8/08 (2013.01);
Abstract

A memory includes S storage blocks, N global bitlines, and a signal amplification circuit. Each of the S storage blocks is connected to the N global bitlines, the N global bitlines are connected to the signal amplification circuit, the signal amplification circuit is configured to amplify electrical signals on the N global bitlines, and each storage block includes N columns of storage units, N local bitlines, and N bitline switches. In each storage block, storage units in an icolumn are connected to an ilocal bitline, the ilocal bitline is connected to an iglobal bitline by using an ibitline switch in the N bitline switches. A memory array is fine-grained, so that ilocal bitlines in the S storage blocks can share one global bitline.


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