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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12183395 B1

PDFFull Text
Date of Patent:
Dec. 31, 2024

Filed:

May. 23, 2022

Silicon-oxide-nitride-oxide-silicon based multi-level non-volatile memory device and methods of operation thereof

Applicant:

Infineon Technologies Llc, San Jose, CA (US);

Inventors:

Venkatraman Prabhakar, Pleasanton, CA (US);

Krishnaswamy Ramkumar, San Jose, CA (US);

Vineet Agrawal, San Jose, CA (US);

Long Hinh, San Jose, CA (US);

Swatilekha Saha, San Jose, CA (US);

Santanu Kumar Samanta, West Bengal, IN;

Michael Amundson, Woodinville, WA (US);

Ravindra M. Kapre, San Jose, CA (US);

Assignee:

Infineon Technologies LLC, San Jose, CA (US);

Attorney:
Primary Examiner:

Han Yang

Int. Cl.
CPC ...
G11C 11/56 (2006.01); G06N 3/065 (2023.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/16 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/792 (2006.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01);
U.S. Cl.
CPC ...
G11C 11/5671 (2013.01); G06N 3/065 (2023.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/16 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/3445 (2013.01); G11C 16/3459 (2013.01); H01L 29/6659 (2013.01); H01L 29/66833 (2013.01); H01L 29/7833 (2013.01); H01L 29/7923 (2013.01); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02);
Abstract

A method of operating a semiconductor inference device that includes the steps of writing one of multiple analog weight values to memory cells of a non-volatile memory (NVM) array, receiving inputs through a bus system, performing multiply accumulate (MAC) operations based on the inputs and the stored analog weight values, converting results of the MAC operations to outputs, and transmitting the outputs through the bus system.

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