The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2024

Filed:

Nov. 07, 2022
Applicant:

Unisantis Electronics Singapore Pte. Ltd., Singapore, SG;

Inventors:

Riichiro Shirota, Hsinchu, TW;

Nozomu Harada, Tokyo, JP;

Koji Sakui, Tokyo, JP;

Masakazu Kakumu, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4097 (2006.01); G11C 11/408 (2006.01); H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
G11C 11/4097 (2013.01); G11C 11/4085 (2013.01); H10B 12/20 (2023.02);
Abstract

A dynamic flash memory is formed by stacking, on a first impurity layer on a P-layer substrate, a first insulating layer, a first material layer, a second insulating layer, a second material layer, a third insulating layer, a third material layer, and a fourth material layer, forming a first hole penetrating these layers on the P-layer substrate, forming a semiconductor pillar by embedding the first hole with a semiconductor, removing the first, second, and third material layers to form second, third, and fourth holes, by oxidizing an outermost surface of the semiconductor pillar exposing in the second, third, and fourth holes to form first, second, and third gate insulating layers, and forming first, second, and third gate conductor layers embedded in the second, third, and fourth holes.


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