The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 31, 2024
Filed:
Apr. 20, 2020
Applicant:
Cirrus Logic International Semiconductor Ltd., Edinburgh, GB;
Inventors:
Michael R. Kobe, Austin, TX (US);
David Kostusiak, Austin, TX (US);
Christian Larsen, Austin, TX (US);
Assignee:
Cirrus Logic Inc., Austin, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/20 (2020.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/20 (2020.01);
Abstract
A method for enforcing design rules in a circuit layout may include providing a circuit schematic for an integrated circuit to a circuit simulator, wherein the circuit layout is derived from a circuit schematic, using the circuit simulator to simulate the circuit schematic and generate simulated electrical parameters for the integrated circuit, and using the simulated electrical parameters to enforce physical design rules when generating the circuit layout based on the simulated electrical parameters.