The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2024

Filed:

Jun. 12, 2023
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Matthew David Pierson, Frisco, TX (US);

Daniel Wu, Plano, TX (US);

Kai Chirca, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01); G06F 9/50 (2006.01); G06F 12/06 (2006.01); G06F 12/0811 (2016.01); G06F 12/0815 (2016.01); G06F 12/0817 (2016.01); G06F 12/0831 (2016.01); G06F 12/084 (2016.01); G06F 12/0855 (2016.01); G06F 12/0875 (2016.01); G06F 12/0891 (2016.01); G06F 12/10 (2016.01); G06F 12/1009 (2016.01); G06F 13/12 (2006.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); H03M 13/01 (2006.01); H03M 13/09 (2006.01); H03M 13/15 (2006.01); H03M 13/27 (2006.01); G06F 12/0846 (2016.01); G06F 12/0862 (2016.01);
U.S. Cl.
CPC ...
G06F 3/0604 (2013.01); G06F 3/0607 (2013.01); G06F 3/0632 (2013.01); G06F 3/064 (2013.01); G06F 3/0658 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 3/0679 (2013.01); G06F 9/30101 (2013.01); G06F 9/30123 (2013.01); G06F 9/3897 (2013.01); G06F 9/4881 (2013.01); G06F 9/5016 (2013.01); G06F 12/0607 (2013.01); G06F 12/0811 (2013.01); G06F 12/0815 (2013.01); G06F 12/0828 (2013.01); G06F 12/0831 (2013.01); G06F 12/084 (2013.01); G06F 12/0855 (2013.01); G06F 12/0857 (2013.01); G06F 12/0875 (2013.01); G06F 12/0891 (2013.01); G06F 12/10 (2013.01); G06F 12/1009 (2013.01); G06F 13/124 (2013.01); G06F 13/1642 (2013.01); G06F 13/1663 (2013.01); G06F 13/1668 (2013.01); G06F 13/4027 (2013.01); H03M 13/015 (2013.01); H03M 13/098 (2013.01); H03M 13/1575 (2013.01); H03M 13/276 (2013.01); H03M 13/2785 (2013.01); G06F 12/0833 (2013.01); G06F 12/0846 (2013.01); G06F 12/0851 (2013.01); G06F 12/0862 (2013.01); G06F 2212/1008 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/1048 (2013.01); G06F 2212/304 (2013.01); G06F 2212/452 (2013.01); G06F 2212/6024 (2013.01); G06F 2212/657 (2013.01);
Abstract

A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.


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