The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 31, 2024
Filed:
Jan. 12, 2023
Infineon Technologies Ag, Neubiberg, DE;
Infineon Technologies AG, Neubiberg, DE;
Abstract
A method for protecting an integrated circuit against reverse engineering including predefining a secret bit, forming a first clocked memory element having a first data input, a first data output and a first clock input in the integrated circuit, forming a second clocked memory element having a second data input, a second data output and a second clock input in the integrated circuit, forming a logic path in the integrated circuit and coupling the first data output to the second data input via the logic path and forming a clock signal line in the integrated circuit and coupling the first clock input to the second clock input via the clock signal line. The logic path and the clock signal line are formed such that their delays are such that, depending on a value of the secret bit, a logic level change of the first clocked memory element with a clock edge of a clock signal on the clock signal line affects a logic level output by the second clocked memory element with the same clock edge of the clock signal, or a logic level change of the first clocked memory element with a clock edge of a clock signal on the clock signal line affects a logic level output by second clocked memory element with any clock edge coming after the next clock edge of the clock signal.