The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2024

Filed:

Jan. 10, 2023
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Kazuaki Terashima, Tokyo, JP;

Atsushi Nakamura, Tokyo, JP;

Rajesh Ghimire, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/28 (2006.01); G06F 7/544 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 13/28 (2013.01); G06F 7/5443 (2013.01); G06F 13/1689 (2013.01);
Abstract

A semiconductor device capable of preventing a sharp variation in current consumption in neural network processing is provided. A dummy circuit outputs dummy data to at least one or more of n number of MAC circuits and causes the at least one or more of n number of MAC circuits to perform a dummy calculation and to output dummy output data. An output-side DMA controller transfers pieces of normal output data from the n number of MAC circuits to a memory, by use of n number of channels, respectively, and does not transfer the dummy output data to the memory. In this semiconductor device, the at least one or more of n number of MAC circuits perform the dummy calculation in a period from a timing at which the output-side DMA controller ends data transfer to the memory to a timing at which the input-side DMA controller starts data transfer from the memory.


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