The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2024

Filed:

Oct. 12, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Dimin Niu, Sunnyvale, CA (US);

Krishna Malladi, San Jose, CA (US);

Hongzhong Zheng, Los Gatos, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 3/06 (2006.01); G06F 11/20 (2006.01);
U.S. Cl.
CPC ...
G06F 11/2094 (2013.01); G06F 3/0619 (2013.01); G06F 3/0635 (2013.01); G06F 3/0659 (2013.01); G06F 3/0688 (2013.01); G06F 2201/82 (2013.01);
Abstract

According to one general aspect, an apparatus may include a plurality of stacked integrated circuit dies that include a memory cell die and a logic die. The memory cell die may be configured to store data at a memory address. The logic die may include an interface to the stacked integrated circuit dies and configured to communicate memory accesses between the memory cell die and at least one external device. The logic die may include a reliability circuit configured to ameliorate data errors within the memory cell die. The reliability circuit may include a spare memory configured to store data, and an address table configured to map a memory address associated with an error to the spare memory. The reliability circuit may be configured to determine if the memory access is associated with an error, and if so completing the memory access with the spare memory.


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