The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2024

Filed:

Dec. 28, 2021
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Veeramanikandan Raju, Bengaluru, IN;

Sudhakar Surendran, Bengaluru, IN;

Anand Kumar G, Bengaluru, IN;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/14 (2006.01); G06F 11/07 (2006.01); G06F 11/22 (2006.01); G06F 11/26 (2006.01); G06F 11/30 (2006.01); G06F 11/34 (2006.01); G06F 11/36 (2006.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); G06F 21/10 (2013.01); G06F 21/60 (2013.01);
U.S. Cl.
CPC ...
G06F 11/1441 (2013.01); G06F 11/0772 (2013.01); G06F 11/0793 (2013.01); G06F 11/1417 (2013.01); G06F 11/2205 (2013.01); G06F 11/2247 (2013.01); G06F 11/2284 (2013.01); G06F 11/26 (2013.01); G06F 11/3051 (2013.01); G06F 11/3055 (2013.01); G06F 11/3423 (2013.01); G06F 11/349 (2013.01); G06F 11/3688 (2013.01); G06F 13/1668 (2013.01); G06F 13/409 (2013.01); G06F 21/107 (2023.08); G06F 21/602 (2013.01);
Abstract

This disclosure relates to an electronic device. The electronic device includes a non-transitory storage device, one or more peripherals, wherein the one or more peripherals are disabled, a processor configured to transmit a request to enable a peripheral of the one or more peripherals, and a power reset manager module. The power reset manager module is configured to receive the request to enable the peripheral. The power reset manager module includes a first memory configured to store, in response to the received request, an indication that peripheral was enabled. The processor is further configured to copy contents of the first memory to the non-transitory storage device and output the indication that the peripheral was enabled as a part of an update procedure.


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