The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2024

Filed:

Feb. 10, 2021
Applicant:

Edwards Vacuum Llc, Sanborn, NY (US);

Inventor:

Kaustubh Kale, Chelmsford, MA (US);

Assignee:

Edwards Vacuum LLC, Sanborn, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
F25B 49/02 (2006.01); F25B 41/20 (2021.01); F25B 41/40 (2021.01); H01L 21/67 (2006.01); H01L 21/687 (2006.01);
U.S. Cl.
CPC ...
F25B 49/02 (2013.01); F25B 41/20 (2021.01); F25B 41/40 (2021.01); H01L 21/67103 (2013.01); F25B 2500/07 (2013.01); F25B 2600/2501 (2013.01); F25B 2700/197 (2013.01); H01L 21/68714 (2013.01);
Abstract

A semiconductor wafer cooling system and method and a pressure regulating apparatus for mitigating pressure increases in a semiconductor wafer conditioning circuit are disclosed. The pressure regulating apparatus comprises: a buffer vessel, the buffer vessel comprising an inlet and outlet channel; wherein the inlet channel is configured in operation to be in fluid communication with a higher pressure location of the semiconductor wafer conditioning circuit, and the outlet channel is configured in operation to be in fluid communication with a lower pressure location. the inlet channel comprises a pressure controlled valve configured to close the inlet channel during normal operation such that the buffer vessel is isolated from the higher pressure location of the conditioning circuit and to open the inlet channel in response to the pressure within the semiconductor conditioning circuit rising above a predetermined level.


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