The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2024

Filed:

Jun. 03, 2022
Applicant:

Nanya Technology Corporation, New Taipei, TW;

Inventor:

Ying-Cheng Chuang, Taoyuan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); H01L 21/77 (2017.01);
U.S. Cl.
CPC ...
H10B 12/488 (2023.02); H10B 12/02 (2023.02); H10B 12/036 (2023.02); H10B 12/038 (2023.02); H10B 12/0387 (2023.02);
Abstract

The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a substrate, forming a metallization layer on the substrate, forming an upper dielectric layer over the metallization layer, forming a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer penetrating the upper dielectric layer and the metallization layer, wherein the first sacrificial layer is aligned with the third sacrificial layer along a first axis, and the second sacrificial layer is free from overlapping the first sacrificial layer and the third sacrificial layer along the first axis, forming a width controlling structure between the first sacrificial layer and the third sacrificial layer, wherein the width controlling structure defines a recess exposing the upper dielectric layer, forming a protective layer within the recess, removing the width controlling structure to expose a portion of the metallization layer.


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