The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2024

Filed:

Jun. 26, 2023
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

Daniel Dinu, Redmond, WA (US);

Juan Carlos Arevalo Baeza, Bellevue, WA (US);

Barry Friemel, Redmond, WA (US);

William Chen, Issaquah, WA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 19/13 (2014.01); G06T 1/20 (2006.01); H04N 19/105 (2014.01); H04N 19/112 (2014.01); H04N 19/124 (2014.01); H04N 19/15 (2014.01); H04N 19/159 (2014.01); H04N 19/186 (2014.01); H04N 19/31 (2014.01); H04N 19/42 (2014.01); H04N 19/43 (2014.01); H04N 19/436 (2014.01); H04N 19/44 (2014.01); H04N 19/46 (2014.01); H04N 19/51 (2014.01); H04N 19/593 (2014.01); H04N 19/61 (2014.01); H04N 19/82 (2014.01); H04N 19/89 (2014.01); H04N 19/91 (2014.01); H04N 19/137 (2014.01); H04N 19/16 (2014.01); H04N 19/172 (2014.01); H04N 19/174 (2014.01); H04N 19/176 (2014.01); H04N 19/184 (2014.01);
U.S. Cl.
CPC ...
H04N 19/13 (2014.11); G06T 1/20 (2013.01); H04N 19/105 (2014.11); H04N 19/124 (2014.11); H04N 19/15 (2014.11); H04N 19/159 (2014.11); H04N 19/186 (2014.11); H04N 19/31 (2014.11); H04N 19/42 (2014.11); H04N 19/43 (2014.11); H04N 19/436 (2014.11); H04N 19/46 (2014.11); H04N 19/51 (2014.11); H04N 19/593 (2014.11); H04N 19/61 (2014.11); H04N 19/82 (2014.11); H04N 19/91 (2014.11); H04N 19/112 (2014.11); H04N 19/137 (2014.11); H04N 19/16 (2014.11); H04N 19/172 (2014.11); H04N 19/174 (2014.11); H04N 19/176 (2014.11); H04N 19/184 (2014.11); H04N 19/44 (2014.11); H04N 19/89 (2014.11);
Abstract

Video decoding innovations for multithreading implementations and graphics processor unit ('GPU') implementations are described. For example, for multithreaded decoding, a decoder uses innovations in the areas of layered data structures, picture extent discovery, a picture command queue, and/or task scheduling for multithreading. Or, for a GPU implementation, a decoder uses innovations in the areas of inverse transforms, inverse quantization, fractional interpolation, intra prediction using waves, loop filtering using waves, memory usage and/or performance-adaptive loop filtering. Innovations are also described in the areas of error handling and recovery, determination of neighbor availability for operations such as context modeling and intra prediction, CABAC decoding, computation of collocated information for direct mode macroblocks in B slices, reduction of memory consumption, implementation of trick play modes, and picture dropping for quality adjustment.


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