The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2024

Filed:

Jun. 09, 2022
Applicant:

Icometrue Company Ltd., Zhubei, TW;

Inventors:

Jin-Yuan Lee, Hsinchu, TW;

Mou-Shiung Lin, Hsinchu, TW;

Assignee:

iCometrue Company Ltd., Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/1776 (2020.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 25/18 (2023.01); H03K 19/173 (2006.01); H03K 19/17728 (2020.01); H03K 19/20 (2006.01); H03K 19/21 (2006.01); H10B 41/00 (2023.01); H10B 63/00 (2023.01);
U.S. Cl.
CPC ...
H03K 19/1776 (2013.01); H01L 23/5386 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 25/18 (2013.01); H03K 19/1737 (2013.01); H03K 19/17728 (2013.01); H10B 41/00 (2023.02); H10B 63/00 (2023.02); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/11 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/81 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/0235 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/0345 (2013.01); H01L 2224/03452 (2013.01); H01L 2224/03912 (2013.01); H01L 2224/11462 (2013.01); H01L 2224/1147 (2013.01); H01L 2224/11849 (2013.01); H01L 2224/13013 (2013.01); H01L 2224/13014 (2013.01); H01L 2224/13023 (2013.01); H01L 2224/13082 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/18 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73259 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/83104 (2013.01); H01L 2224/83862 (2013.01); H01L 2224/92225 (2013.01); H01L 2224/94 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/1437 (2013.01); H01L 2924/1443 (2013.01); H01L 2924/18161 (2013.01); H03K 19/20 (2013.01); H03K 19/21 (2013.01);
Abstract

A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.


Find Patent Forward Citations

Loading…