The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2024

Filed:

Jun. 24, 2020
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Hiroki Inoue, Atsugi, JP;

Kousuke Sasaki, Atsugi, JP;

Yuto Yakubo, Atsugi, JP;

Kei Takahashi, Isehara, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H02M 3/156 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); H02H 7/18 (2006.01);
U.S. Cl.
CPC ...
H02M 3/156 (2013.01); H01L 27/1225 (2013.01); H01L 29/7869 (2013.01); H01L 29/78696 (2013.01); H02H 7/18 (2013.01);
Abstract

A novel oscillator, an amplifier circuit, an inverter circuit, an amplifier circuit, a battery control circuit, a battery protection circuit, a power storage device, a semiconductor device, an electric device, and the like are provided. The semiconductor device includes an oscillator including a first transistor containing a metal oxide, and a second transistor to a fifth transistor, in which a first potential is supplied to a gate of the second transistor and a gate of the third transistor when the first transistor is turned on, and the first potential is held when the first transistor is turned off. The oscillator supplies a first signal based on the first potential to a first circuit. The first circuit performs at least one of shaping and amplification on the first signal. The second transistor and the fourth transistor are connected in series, and the third transistor and the fifth transistor are connected in series. A source or a drain of the third transistor is electrically connected to a gate of the fourth transistor, and a source or a drain of the fourth transistor is electrically connected to the gate of the third transistor.


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