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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12176202 B1

PDFFull Text
Date of Patent:
Dec. 24, 2024

Filed:

Oct. 08, 2020

Manufacture method of a high-resistivity silicon handle wafer for a hybrid substrate structure

Applicant:

Okmetic Oy, Vantaa, FI;

Inventors:

Päivi Sievilä, Espoo, FI;

Samuli Sievänen, Helsinki, FI;

Jukka-Pekka Lähteenmäki, Vantaa, FI;

Karri Mannermaa, Vantaa, FI;

Joel Salmi, Helsinki, FI;

Atte Haapalinna, Espoo, FI;

Assignee:

OKMETIC OY, Vantaa, FI;

Attorney:

Thomas | Horstemeyer, LLP

Primary Examiner:

Kevin Parendo

Int. Cl.
CPC ...
H01L 21/02 (2006.01); B24B 49/12 (2006.01); B24B 51/00 (2006.01); H01L 21/304 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02013 (2013.01); B24B 49/12 (2013.01); B24B 51/00 (2013.01); H01L 21/02024 (2013.01); H01L 21/304 (2013.01);
Abstract

The application relates to a manufacture method of a high-resistivity silicon handle wafer for a hybrid substrate structure. The method comprises a step of producing the wafer having a crystal orientation identifier and a certain thickness. The method further comprises a step of thinning the produced wafer from the certain thickness to a desired thickness of the wafer in order to obtain the thinned wafer. The method further comprises a step of providing a surface passivation layer having a certain layer thickness on a front surface of the thinned wafer. The method further comprises a step of polishing the passivation layer from the certain layer thickness to a desired final layer thickness of the passivation layer so that the polished front surface of the wafer enables active layer bonding in order to form the hybrid substrate structure.

Find Patent Forward Citations

Sievilä, Päivi. (2024). Manufacture method of a high-resistivity silicon handle wafer for a hybrid substrate structure (U.S. Patent No. 12176202). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12176202

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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