Semiconductor memory device and method of perfomring a multi-level sensing operation

Abstract

The present technology relates to a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device includes a memory block including a plurality of memory cells programmed to an erase state and a plurality of program states, a voltage generation circuit configured to generate a read voltage to be applied to word lines of the memory block during a read operation, and a read and write circuit connected to bit lines of the memory block and configured to latch data by sensing a potential level of a sensing node based on a cell current of the memory cells in a predetermined time unit during the read operation, wherein the read voltage is applied to the word lines consecutively in a predetermined period and gradually increases according to a time in the predetermined period.