Hardware acceleration method and system based on scale-invariant feature transform algorithm

Abstract

A hardware acceleration method and system based on a scale-invariant feature transform algorithm in the field of hardware acceleration design of algorithms is disclosed. The architecture mainly includes two parts: keypoint detection and descriptor generation. Four buffers between these two parts are ping-ponged to increase the system processing speed. In the keypoint detection part, firstly, multi-layer Gaussian pyramid and Gaussian difference pyramid are calculated in parallel; through parallel calculation, the keypoints and gradient magnitudes and orientations are obtained. In the descriptor generation part, a keypoint region division strategy based on the circular keypoint region is provided, and the parallel calculation of a main orientation calculation module and a descriptor generation module are implemented. Finally, the output is obtained through descriptor rearrangement and dimensionality reduction module.